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authorHanhui <sylixos@gmail.com>2019-07-03 15:02:58 (GMT)
committer Hanhui <sylixos@gmail.com>2019-06-19 09:04:04 (GMT)
commit03404d8e11e2fc7efed84915bf1804c48b87d9b0 (patch)
treeb46de1f333b1b525d8f9f54d339aee402f24927d
parent2dd35ef0209c32595962f924f6445673104e568f (diff)
downloadAIC-OS-03404d8e11e2fc7efed84915bf1804c48b87d9b0.zip
Fixed ARM32 architecture to manually enable floating point errors.
-rw-r--r--SylixOS/arch/arm/fpu/armFpu.c3
-rw-r--r--SylixOS/arch/arm/fpu/vfp9/armVfp9Asm.S12
-rw-r--r--SylixOS/arch/arm/fpu/vfpv3/armVfpV3Asm.S11
3 files changed, 16 insertions, 10 deletions
diff --git a/SylixOS/arch/arm/fpu/armFpu.c b/SylixOS/arch/arm/fpu/armFpu.c
index 16f445d..a495ddb 100644
--- a/SylixOS/arch/arm/fpu/armFpu.c
+++ b/SylixOS/arch/arm/fpu/armFpu.c
@@ -103,8 +103,7 @@ VOID archFpuPrimaryInit (CPCHAR pcMachineName, CPCHAR pcFpuName)
_G_fpuCtxInit.FPUCTX_fpuctxContext.FPUCTX_uiFpsid = (UINT32)ARM_VFP_HW_SID(_G_pfpuop);
ARM_VFP_SAVE(_G_pfpuop, (PVOID)&_G_fpuCtxInit);
-
- _G_fpuCtxInit.FPUCTX_fpuctxContext.FPUCTX_uiFpexc = 0x00000000; /* disable VFP */
+
_G_fpuCtxInit.FPUCTX_fpuctxContext.FPUCTX_uiFpscr = 0x01000000; /* Set FZ bit in VFP */
/* Do not enable FPU */
ARM_VFP_DISABLE(_G_pfpuop);
diff --git a/SylixOS/arch/arm/fpu/vfp9/armVfp9Asm.S b/SylixOS/arch/arm/fpu/vfp9/armVfp9Asm.S
index 2a589e7..b15b131 100644
--- a/SylixOS/arch/arm/fpu/vfp9/armVfp9Asm.S
+++ b/SylixOS/arch/arm/fpu/vfp9/armVfp9Asm.S
@@ -50,7 +50,7 @@ FUNC_DEF(armVfp9Sid)
FUNC_END()
FUNC_DEF(armVfp9Enable)
- MOV R1, #0x40000000 ;/* Set Neon/VFP Enable bit */
+ MOV R1, #(1 << 30) ;/* Set Neon/VFP Enable bit */
FMXR FPEXC, R1 ;/* FPEXC, clear others. */
BX LR
FUNC_END()
@@ -100,12 +100,15 @@ FUNC_DEF(armVfp9IsEnable)
;*********************************************************************************************************/
MACRO_DEF(VFP9_SAVE_CTRL)
- FMRX R1, FPSCR
- STR R1, [R0, #VFP_FPSCR]
-
FMRX R1, FPEXC
+ ORR R1, R1, #(1 << 30)
+ FMXR FPEXC, R1
+
STR R1, [R0, #VFP_FPEXC]
+ FMRX R2, FPSCR
+ STR R2, [R0, #VFP_FPSCR]
+
FMRX R2, FPINST
STR R2, [R0, #VFP_FPINST]
@@ -125,6 +128,7 @@ MACRO_DEF(VFP9_SAVE_CTRL)
MACRO_DEF(VFP9_RESTORE_CTRL)
LDR R1, [R0, #VFP_FPEXC]
+ ORR R1, R1, #(1 << 30)
FMXR FPEXC, R1
LDR R2, [R0, #VFP_FPINST]
diff --git a/SylixOS/arch/arm/fpu/vfpv3/armVfpV3Asm.S b/SylixOS/arch/arm/fpu/vfpv3/armVfpV3Asm.S
index 6386973..d220583 100644
--- a/SylixOS/arch/arm/fpu/vfpv3/armVfpV3Asm.S
+++ b/SylixOS/arch/arm/fpu/vfpv3/armVfpV3Asm.S
@@ -71,12 +71,15 @@
;*********************************************************************************************************/
MACRO_DEF(VFPv3_SAVE_CTRL)
- FMRX R1, FPSCR
- STR R1, [R0, #VFP_FPSCR] ;/* FPSCR */
-
FMRX R1, FPEXC
+ ORR R1, R1, #(1 << 30)
+ FMXR FPEXC, R1
+
STR R1, [R0, #VFP_FPEXC] ;/* FPEXC */
+ FMRX R2, FPSCR
+ STR R2, [R0, #VFP_FPSCR] ;/* FPSCR */
+
ORR R1, R1, #((1 << 28) | (1 << 31))
FMXR FPEXC, R1 ;/* Set FPEXC.EX=1 and FPEXC.FP2V=1 */
@@ -102,7 +105,7 @@ MACRO_DEF(VFPv3_SAVE_CTRL)
MACRO_DEF(VFPv3_RESTORE_CTRL)
FMRX R1, FPEXC
- ORR R1, R1, #((1 << 28) | (1 << 31))
+ ORR R1, R1, #((1 << 28) | (1 << 30) | (1 << 31))
FMXR FPEXC, R1 ;/* Set FPEXC.EX=1 and FPEXC.FP2V=1 */
FMRX R1, FPEXC ;/* Read back the FPEXC register */