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authorHanhui <sylixos@gmail.com>2019-06-26 07:24:00 (GMT)
committer Hanhui <sylixos@gmail.com>2019-06-19 09:03:32 (GMT)
commitc6a85524f36f04e32a0e4664e90ff190d00055cc (patch)
tree1ee675755a01cb861e39a83653511a9d202ca10e
parent093720f12a0604b713cd6a071019c2ed12aa93b4 (diff)
downloadAIC-OS-c6a85524f36f04e32a0e4664e90ff190d00055cc.zip
Enhanced compatibility with old Celeron(TM) processors.
-rw-r--r--SylixOS/arch/x86/apic/x86IoApic.c23
-rw-r--r--SylixOS/arch/x86/apic/x86LocalApic.c32
-rw-r--r--SylixOS/arch/x86/common/x86CpuId.c140
-rw-r--r--SylixOS/arch/x86/common/x86CpuId.h98
-rw-r--r--SylixOS/arch/x86/pentium/x86Pentium.c20
-rw-r--r--SylixOS/config/cpu/cpu_cfg_x86.h2
6 files changed, 18 insertions, 297 deletions
diff --git a/SylixOS/arch/x86/apic/x86IoApic.c b/SylixOS/arch/x86/apic/x86IoApic.c
index d2a689d..beff441 100644
--- a/SylixOS/arch/x86/apic/x86IoApic.c
+++ b/SylixOS/arch/x86/apic/x86IoApic.c
@@ -496,18 +496,17 @@ static INT __x86IoApicInit (PX86_IOAPIC_INTR pIoApicIntr)
* hardwired to FSB delivery.
*/
if (((pIoApicIntr->IOAPIC_uiVersion & IOAPIC_VERSION_MASK) >= 0x20)) {
- if (X86_FEATURE_PROCESSOR_FAMILY >= X86_FAMILY_PENTIUM4) {
- /*
- * Pentium4 and later use FSB for interrupt delivery
- */
- __x86IoApicRegSet(pIoApicIntr, IOAPIC_BOOT, IOAPIC_DT_FS);
-
- } else {
- /*
- * Pentium up to and including P6 use APIC bus
- */
- __x86IoApicRegSet(pIoApicIntr, IOAPIC_BOOT, IOAPIC_DT_APIC);
- }
+#if LW_CFG_CPU_X86_APIC_BUS_INT > 0
+ /*
+ * Pentium up to and including P6 use APIC bus
+ */
+ __x86IoApicRegSet(pIoApicIntr, IOAPIC_BOOT, IOAPIC_DT_APIC);
+#else
+ /*
+ * Pentium4 and later use FSB for interrupt delivery
+ */
+ __x86IoApicRegSet(pIoApicIntr, IOAPIC_BOOT, IOAPIC_DT_FS);
+#endif /* X86_APIC_BUS_INT > 0 */
}
uiRteValue = IOAPIC_EDGE | /* 边沿信号触发 */
diff --git a/SylixOS/arch/x86/apic/x86LocalApic.c b/SylixOS/arch/x86/apic/x86LocalApic.c
index 9c559e5..56c4f43 100644
--- a/SylixOS/arch/x86/apic/x86LocalApic.c
+++ b/SylixOS/arch/x86/apic/x86LocalApic.c
@@ -317,43 +317,11 @@ static VOID __x86LocalApicEnable (PX86_LOAPIC_INTR pLoApicIntr, BOOL bEnable)
INT x86LocalApicInit (UINT *puiLocalApicIntNr)
{
PX86_LOAPIC_INTR pLoApicIntr = &_G_x86LocalApicIntrs[LW_CPU_GET_CUR_ID()];
- UINT64 ui64ApicBase;
INT iCoreNum;
pLoApicIntr->LOAPIC_pcBase = (CHAR *)LOCAL_APIC_BASE;
pLoApicIntr->LOAPIC_uiIntMask = 0;
- if (X86_FEATURE_HAS_APIC && (X86_FEATURE_PROCESSOR_FAMILY != X86_FAMILY_PENTIUM)) {
- CHAR *pcMpApicLoBase;
- INT i;
-
- x86PentiumMsrGet(X86_MSR_APICBASE, (UINT64 *)&ui64ApicBase);
- pcMpApicLoBase = (CHAR *)((ULONG)ui64ApicBase & LOAPIC_BASE_MASK);
-
- if (pLoApicIntr->LOAPIC_pcBase != pcMpApicLoBase) {
- ui64ApicBase &= ~LOAPIC_BASE_MASK;
- ui64ApicBase |= LOCAL_APIC_BASE;
- }
-
- /*
- * Enable the Local APIC explicitly by making sure
- * it is disabled first. A toggle will make sure
- * interrupts are cleared.
- */
- ui64ApicBase &= ~(LOAPIC_GLOBAL_ENABLE); /* Clear Enable bit */
- x86PentiumMsrSet(X86_MSR_APICBASE, &ui64ApicBase);
-
- /*
- * Delays 50usec
- */
- for (i = 0; i < 70; i++) { /* 70*720 ~= 50.4usec */
- bspDelay720Ns(); /* 720ns */
- }
-
- ui64ApicBase |= LOAPIC_GLOBAL_ENABLE; /* Set Enable bit */
- x86PentiumMsrSet(X86_MSR_APICBASE, &ui64ApicBase);
- }
-
/*
* Remember the original state: SVR, LINT0, LINT1 for now
*/
diff --git a/SylixOS/arch/x86/common/x86CpuId.c b/SylixOS/arch/x86/common/x86CpuId.c
index 50799e4..239fb48 100644
--- a/SylixOS/arch/x86/common/x86CpuId.c
+++ b/SylixOS/arch/x86/common/x86CpuId.c
@@ -52,63 +52,6 @@
*********************************************************************************************************/
static UINT64 _G_ui64X86CpuIdFreq = 1000000000ULL; /* CPU 主频, 缺省为 1GHz */
-static X86_CPUID_ENTRY _G_x86CpuIdTable[] = { /* CPUID 条目表 */
- {X86_CPUID_PENTIUM, X86_FAMILY_PENTIUM},
- {X86_CPUID_PENTIUM4, X86_FAMILY_PENTIUM4},
- {X86_CPUID_CORE, X86_FAMILY_CORE},
- {X86_CPUID_CORE2, X86_FAMILY_CORE},
- {X86_CPUID_CORE2_DUO, X86_FAMILY_CORE},
- {X86_CPUID_XEON_5400, X86_FAMILY_NEHALEM},
- {X86_CPUID_XEON_7400, X86_FAMILY_NEHALEM},
- {X86_CPUID_XEON_5500, X86_FAMILY_NEHALEM},
- {X86_CPUID_XEON_C5500, X86_FAMILY_NEHALEM},
- {X86_CPUID_XEON_5600, X86_FAMILY_NEHALEM},
- {X86_CPUID_XEON_7500, X86_FAMILY_NEHALEM},
- {X86_CPUID_COREI5_I7M, X86_FAMILY_NEHALEM},
- {X86_CPUID_XEON_32NM, X86_FAMILY_NEHALEM},
- {X86_CPUID_ATOM, X86_FAMILY_ATOM},
- {X86_CPUID_SANDYBRIDGE, X86_FAMILY_SANDYBRIDGE},
- {X86_CPUID_CEDARVIEW, X86_FAMILY_ATOM},
- {X86_CPUID_SILVERMONT, X86_FAMILY_ATOM},
-
- {X86_CPUID_HASWELL_CLIENT, X86_FAMILY_HASWELL},
- {X86_CPUID_HASWELL_SERVER, X86_FAMILY_HASWELL},
- {X86_CPUID_HASWELL_ULT, X86_FAMILY_HASWELL},
- {X86_CPUID_CRYSTAL_WELL, X86_FAMILY_HASWELL},
-
- {X86_CPUID_MINUTEIA, X86_FAMILY_MINUTEIA},
-
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY},
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY},
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY},
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY},
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY},
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY},
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY},
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY},
- {X86_CPUID_DUMMY, X86_CPUID_DUMMY}};
-
-static INT _G_iX86CpuEntriesNr = \
- sizeof(_G_x86CpuIdTable) / sizeof(X86_CPUID_ENTRY); /* CPUID 条目数 */
-
-const static CHAR *_G_pcX86CpuFamilyNames[] = { /* CPU 家族名字表 */
- "Not Supported", /* 0 */
- "Not Supported", /* 1 */
- "Pentium", /* 2 */
- "Not Supported", /* 3 */
- "Not Supported", /* 4 */
- "Pentium 4", /* 5 */
- "Core", /* 6 */
- "Atom", /* 7 */
- "Nehalem", /* 8 */
- "Sandy Bridge", /* 9 */
- "Haswell", /* 10 */
- "Quark" /* 11 */
-};
-
-const static INT _G_iCpuFamilyNr = \
- sizeof(_G_pcX86CpuFamilyNames) / sizeof(CHAR *); /* CPU 家族名字数 */
-
const static CHAR *_G_pcX86CacheTypes[] = { /* CACHE 类型表 */
"Null", /* 0 */
"Data", /* 1 */
@@ -153,7 +96,6 @@ X86_CPU_FEATURE _G_x86CpuFeature = { /* 全局
.CPUF_stCacheFlushBytes = X86_CLFLUSH_DEF_BYTES, /* CLFLUSH 字节数 */
.CPUF_bHasCLFlush = LW_FALSE, /* Has CLFLUSH inst? */
.CPUF_bHasAPIC = LW_FALSE, /* Has APIC on chip? */
- .CPUF_uiProcessorFamily = X86_FAMILY_UNSUPPORTED, /* Processor Family */
.CPUF_bHasX87FPU = LW_FALSE, /* Has X87 FPU? */
.CPUF_bHasSSE = LW_FALSE, /* Has SSE? */
.CPUF_bHasSSE2 = LW_FALSE, /* Has SSE? */
@@ -257,32 +199,6 @@ X86_CPUID *x86CpuIdGet (VOID)
return (&_G_x86CpuId);
}
/*********************************************************************************************************
-** 函数名称: x86CpuIdAdd
-** 功能描述: 增加一个新的 X86_CPUID_ENTRY 到支持的 CPUID 条目表
-** 输 入 : pentry CPUID 条目
-** 输 出 : ERROR CODE
-** 全局变量:
-** 调用模块:
-*********************************************************************************************************/
-INT x86CpuIdAdd (X86_CPUID_ENTRY *pentry)
-{
- X86_CPUID_ENTRY *pcur = LW_NULL;
- INT i;
- INT iError = PX_ERROR;
-
- for (i = 0; i < _G_iX86CpuEntriesNr; i++) {
- pcur = &_G_x86CpuIdTable[i];
- if (pcur->signature == X86_CPUID_DUMMY) {
- pcur->signature = pentry->signature;
- pcur->family = pentry->family;
- iError = ERROR_NONE;
- break;
- }
- }
-
- return (iError);
-}
-/*********************************************************************************************************
** 函数名称: x86CpuIdOverride
** 功能描述: 覆盖 CPU 特性
** 输 入 : pentries 覆盖的 CPUID 条目
@@ -343,7 +259,6 @@ VOID x86CpuIdProbe (VOID)
X86_CPUID_ECX_CACHE_PARAMS cacheEcx[4];
X86_CPUID_EDX_FEATURES features;
X86_CPUID_ECX_FEATURES extendedFeatures;
- UINT uiCpuId;
CHAR *pcLine;
INT i;
CHAR cTemp[256];
@@ -354,22 +269,6 @@ VOID x86CpuIdProbe (VOID)
extendedFeatures.value = pcpuid->std.featuresEcx;
/*
- * 识别 Intel 处理器家族类型码
- */
- uiCpuId = pcpuid->std.signature & (X86_CPUID_FAMILY | X86_CPUID_MODEL | X86_CPUID_EXT_MODEL);
-
- for (i = 0; i < _G_iX86CpuEntriesNr; i++) {
- if (_G_x86CpuIdTable[i].signature == uiCpuId) {
- pcpufeature->CPUF_uiProcessorFamily = _G_x86CpuIdTable[i].family;
- break;
- }
- }
-
- if (pcpufeature->CPUF_uiProcessorFamily == X86_FAMILY_UNSUPPORTED) {
- pcpufeature->CPUF_uiProcessorFamily = X86_FAMILY_PENTIUM;
- }
-
- /*
* 识别 CPU 名字
*/
if (pcpuid->ext.highestExtValue >= 0x80000002) {
@@ -471,7 +370,6 @@ VOID x86CpuIdProbe (VOID)
VOID x86CpuIdShow (VOID)
{
X86_CPUID *pcpuid = &_G_x86CpuId;
- X86_CPUID_ENTRY *pentry;
X86_CPUID_INFO info;
X86_CPUID_VERSION version;
X86_CPUID_EDX_FEATURES features;
@@ -512,11 +410,8 @@ VOID x86CpuIdShow (VOID)
X86_CPUID_EAX_VPADRSIZES_PARAMS vpadrEax;
UINT64 ulCpuSerial;
- CHAR *pcCpuTypeName = LW_NULL;
CHAR *pcLine;
- UINT uiX86Processor = X86_FAMILY_UNSUPPORTED;
- INT i, iCpuIdMask;
-
+ INT i;
lib_bzero((VOID *)cacheEax, 4 * sizeof(X86_CPUID_EAX_CACHE_PARAMS));
lib_bzero((VOID *)cacheEbx, 4 * sizeof(X86_CPUID_EAX_CACHE_PARAMS));
@@ -566,39 +461,6 @@ VOID x86CpuIdShow (VOID)
version.field.stepid,
version.field.family, version.field.familyExt);
- switch ((INT)version.field.type) {
-
- case X86_CPUID_ORIG:
- pcCpuTypeName = "original OEM";
- break;
-
- case X86_CPUID_OVERD:
- pcCpuTypeName = "overdrive";
- break;
-
- case X86_CPUID_DUAL:
- pcCpuTypeName = "dual";
- break;
-
- default:
- pcCpuTypeName = "<unknown>";
- break;
- }
-
- iCpuIdMask = X86_CPUID_FAMILY | X86_CPUID_MODEL | X86_CPUID_EXT_MODEL;
- for (i = 0; i < _G_iX86CpuEntriesNr; i++) {
- pentry = &_G_x86CpuIdTable[i];
- if ((pentry->signature & iCpuIdMask) == (pcpuid->std.signature & iCpuIdMask)) {
- uiX86Processor = pentry->family;
- break;
- }
- }
-
- printf(" x86 processor architecture is %s, type %s\n",
- ((uiX86Processor <= _G_iCpuFamilyNr) && (uiX86Processor != X86_FAMILY_UNSUPPORTED)) ?
- _G_pcX86CpuFamilyNames[uiX86Processor] : "unsupported",
- pcCpuTypeName);
-
if (features.field.psnum) {
ulCpuSerial = (UINT64)pcpuid->std.serialNo64[0] << 32 | pcpuid->std.serialNo64[1];
printf(" CPU serial number: %lld\n", ulCpuSerial);
diff --git a/SylixOS/arch/x86/common/x86CpuId.h b/SylixOS/arch/x86/common/x86CpuId.h
index 06d0ef7..aac4b66 100644
--- a/SylixOS/arch/x86/common/x86CpuId.h
+++ b/SylixOS/arch/x86/common/x86CpuId.h
@@ -188,92 +188,6 @@
#define X86_CPUID_EXT_MODEL_SANDYBRIDGE 0x00020000
/*********************************************************************************************************
- CPU TYPE
-*********************************************************************************************************/
-
-#define X86_CPUID_ORIG 0x00000000 /* Type: original OEM */
-#define X86_CPUID_OVERD 0x00001000 /* Type: overdrive */
-#define X86_CPUID_DUAL 0x00002000 /* Type: dual */
-
-/*********************************************************************************************************
- CPUID definitions
-*********************************************************************************************************/
-
-#define X86_CPUID_UNSUPPORTED 0xffffffff /* Family: not supported */
-
-/*********************************************************************************************************
- Pentium microarchitecture CPUIDs
-*********************************************************************************************************/
-
-#define X86_CPUID_PENTIUM 0x00000500 /* Family: Pentium */
-#define X86_CPUID_MINUTEIA 0x00000590 /* Family: MinuteIA/Quark */
-#define X86_CPUID_PENTIUM4 0x00000000 /* Extended family: PENTIUM4 */
-
-/*********************************************************************************************************
- Core microarchitecture CPUIDs
-*********************************************************************************************************/
-
-#define X86_CPUID_CORE 0x000006e0 /* Core Solo/Duo */
-#define X86_CPUID_CORE2 0x000006f0 /* Core2 */
-#define X86_CPUID_CORE2_DUO 0x00010670 /* Core2 Duo */
-#define X86_CPUID_XEON_5400 0x00010670 /* Xeon 52xx/54xx */
-#define X86_CPUID_XEON_7400 0x000106d0 /* Xeon 74xx Core2 */
-
-/*********************************************************************************************************
- Nehalem microarchitecture CPUIDs
-*********************************************************************************************************/
-
-#define X86_CPUID_XEON_5500 0x000106a0 /* Xeon 55xx */
-#define X86_CPUID_XEON_C5500 0x000106e0 /* Xeon C35xx/C55xx */
-#define X86_CPUID_XEON_5600 0x000206c0 /* Xeon 56xx */
-#define X86_CPUID_XEON_7500 0x000206e0 /* Xeon 65xx/75xx */
-#define X86_CPUID_XEON_32NM 0x000206f0 /* Xeon 65xx/75xx 32 NM */
-#define X86_CPUID_COREI5_I7M 0x00020650 /* Arrandale i3 or i5/i7 Mobile 6xx/5xx */
-
-/*********************************************************************************************************
- Atom microarchitecture CPUIDs
-*********************************************************************************************************/
-
-#define X86_CPUID_ATOM 0x000106c0 /* Atom */
-#define X86_CPUID_CEDARVIEW 0x00030660 /* Atom CedarView CPU N2800 */
-#define X86_CPUID_SILVERMONT 0x00030672 /* Atom Silvermont CPU */
-
-/*********************************************************************************************************
- Sandy Bridge microarchitecture CPUIDs
-*********************************************************************************************************/
-
-#define X86_CPUID_SANDYBRIDGE 0x000206a0 /* SandyBridge */
-
-/*********************************************************************************************************
- Haswell microarchitecture CPUIDs
-*********************************************************************************************************/
-
-#define X86_CPUID_HASWELL_CLIENT 0x000306c0 /* Haswell Client */
-#define X86_CPUID_HASWELL_SERVER 0x000306f0 /* Haswell Server */
-#define X86_CPUID_HASWELL_ULT 0x00040650 /* Haswell ULT */
-#define X86_CPUID_CRYSTAL_WELL 0x00040660 /* Crystal Well */
-
-/*********************************************************************************************************
- Dummy entry
-*********************************************************************************************************/
-
-#define X86_CPUID_DUMMY 0 /* Dummy CPUID entry */
-
-/*********************************************************************************************************
- CPU FAMILY
-*********************************************************************************************************/
-
-#define X86_FAMILY_UNSUPPORTED 0 /* CPU FAMILY: Not supported */
-#define X86_FAMILY_PENTIUM 2 /* CPU FAMILY: Pentium/P5 */
-#define X86_FAMILY_PENTIUM4 5 /* CPU FAMILY: Pentium4/P7 */
-#define X86_FAMILY_CORE 6 /* CPU FAMILY: Core/Core2 */
-#define X86_FAMILY_ATOM 7 /* CPU FAMILY: Atom */
-#define X86_FAMILY_NEHALEM 8 /* CPU FAMILY: Nehalem */
-#define X86_FAMILY_SANDYBRIDGE 9 /* CPU FAMILY: Sandy Bridge */
-#define X86_FAMILY_HASWELL 10 /* CPU FAMILY: Haswell */
-#define X86_FAMILY_MINUTEIA 11 /* CPU FAMILY: MinuteIA/Quark */
-
-/*********************************************************************************************************
CPU feature override flags
*********************************************************************************************************/
@@ -319,15 +233,6 @@ typedef struct {
} X86_CPUID_OVERRIDE;
/*********************************************************************************************************
- CPUID signature table entry structure
-*********************************************************************************************************/
-
-typedef struct {
- UINT32 signature;
- UINT32 family;
-} X86_CPUID_ENTRY;
-
-/*********************************************************************************************************
CPUID standard features
*********************************************************************************************************/
@@ -872,7 +777,6 @@ typedef struct {
INT CPUF_iDCacheWaySize; /* I-Cache way size */
BOOL CPUF_bHasCLFlush; /* Has CLFLUSH inst? */
BOOL CPUF_bHasAPIC; /* Has APIC on chip? */
- UINT CPUF_uiProcessorFamily; /* Processor Family */
BOOL CPUF_bHasX87FPU; /* Has X87 FPU? */
BOOL CPUF_bHasSSE; /* Has SSE? */
BOOL CPUF_bHasSSE2; /* Has SSE? */
@@ -895,7 +799,6 @@ extern X86_CPU_FEATURE _G_x86CpuFeature;
#define X86_FEATURE_DCACHE_WAY_SIZE _G_x86CpuFeature.CPUF_iDCacheWaySize
#define X86_FEATURE_HAS_CLFLUSH _G_x86CpuFeature.CPUF_bHasCLFlush
#define X86_FEATURE_HAS_APIC _G_x86CpuFeature.CPUF_bHasAPIC
-#define X86_FEATURE_PROCESSOR_FAMILY _G_x86CpuFeature.CPUF_uiProcessorFamily
#define X86_FEATURE_HAS_X87FPU _G_x86CpuFeature.CPUF_bHasX87FPU
#define X86_FEATURE_HAS_SSE _G_x86CpuFeature.CPUF_bHasSSE
#define X86_FEATURE_HAS_SSE2 _G_x86CpuFeature.CPUF_bHasSSE2
@@ -917,7 +820,6 @@ extern X86_CPUID *x86CpuIdGet(VOID);
extern VOID x86CpuIdProbe(VOID);
extern VOID x86CpuIdShow(VOID);
-extern INT x86CpuIdAdd(X86_CPUID_ENTRY *pentry);
extern INT x86CpuIdOverride(X86_CPUID_OVERRIDE *pentries, INT iCount);
extern UINT8 x86CpuIdBitField(UINT8 ucFullId, UINT8 ucMaxSubIdValue, UINT8 ucShiftCount);
diff --git a/SylixOS/arch/x86/pentium/x86Pentium.c b/SylixOS/arch/x86/pentium/x86Pentium.c
index 13550f3..5493830 100644
--- a/SylixOS/arch/x86/pentium/x86Pentium.c
+++ b/SylixOS/arch/x86/pentium/x86Pentium.c
@@ -53,10 +53,7 @@ VOID x86PentiumMtrrEnable (VOID)
X86_CR_REG uiOldCr4;
#if LW_CFG_CPU_WORD_LENGHT == 32
- /*
- * Not available for MinuteIA
- */
- if (X86_FEATURE_PROCESSOR_FAMILY == X86_FAMILY_MINUTEIA) {
+ if (!X86_FEATURE_HAS_MTRR) {
return;
}
#endif /* LW_CFG_CPU_WORD_LENGHT == 32*/
@@ -100,10 +97,7 @@ VOID x86PentiumMtrrDisable (VOID)
X86_CR_REG uiOldCr4;
#if LW_CFG_CPU_WORD_LENGHT == 32
- /*
- * Not available for MinuteIA
- */
- if (X86_FEATURE_PROCESSOR_FAMILY == X86_FAMILY_MINUTEIA) {
+ if (!X86_FEATURE_HAS_MTRR) {
return;
}
#endif /* LW_CFG_CPU_WORD_LENGHT == 32*/
@@ -149,10 +143,7 @@ INT x86PentiumMtrrGet (PX86_MTRR pMtrr)
INTREG iregInterLevel;
#if LW_CFG_CPU_WORD_LENGHT == 32
- /*
- * Not available for MinuteIA
- */
- if (X86_FEATURE_PROCESSOR_FAMILY == X86_FAMILY_MINUTEIA) {
+ if (!X86_FEATURE_HAS_MTRR) {
return (PX_ERROR);
}
#endif /* LW_CFG_CPU_WORD_LENGHT == 32*/
@@ -206,10 +197,7 @@ INT x86PentiumMtrrSet (PX86_MTRR pMtrr)
INTREG iregInterLevel;
#if LW_CFG_CPU_WORD_LENGHT == 32
- /*
- * Not available for MinuteIA
- */
- if (X86_FEATURE_PROCESSOR_FAMILY == X86_FAMILY_MINUTEIA) {
+ if (!X86_FEATURE_HAS_MTRR) {
return (PX_ERROR);
}
#endif /* LW_CFG_CPU_WORD_LENGHT == 32*/
diff --git a/SylixOS/config/cpu/cpu_cfg_x86.h b/SylixOS/config/cpu/cpu_cfg_x86.h
index ddd532b..f54f698 100644
--- a/SylixOS/config/cpu/cpu_cfg_x86.h
+++ b/SylixOS/config/cpu/cpu_cfg_x86.h
@@ -53,6 +53,8 @@
/* 老式奔腾处理器 (1, 2, 3, 4) */
#define LW_CFG_CPU_X86_NO_PAUSE 0 /* 不支持 PAUSE 指令 */
#define LW_CFG_CPU_X86_NO_HLT 0 /* 不支持 HLT 指令 */
+#define LW_CFG_CPU_X86_APIC_BUS_INT 0 /* 使用 APIC BUS 而不是前端总线*/
+ /* 投递中断(老式奔腾 1, 2, 3) */
/*********************************************************************************************************
CPU 字长与整型大小端定义