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authorHanhui <hanhui@acoinfo.com>2020-12-26 13:21:56 (GMT)
committer Hanhui <hanhui@acoinfo.com>2020-12-26 13:21:56 (GMT)
commit8a571ac98ee9e71a43f3fed665eacf366c9b60dc (patch)
tree0d9a3ce91f9a48b87bd2ae4c17311c0a96f199f3 /SylixOS
parent87ba014a6a1d97026c4f1cb7f545d0211e1b5ab5 (diff)
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Add LS3A4000 support.
Diffstat (limited to 'SylixOS')
-rw-r--r--SylixOS/arch/mips/common/mipsCpuProbe.c4
-rw-r--r--SylixOS/arch/mips/mm/cache/loongson3x/mipsCacheLs3x.c5
-rw-r--r--SylixOS/arch/mips/mm/cache/mipsCacheCommon.c4
-rw-r--r--SylixOS/arch/mips/mm/mipsCache.c6
-rw-r--r--SylixOS/arch/mips/mm/mmu/mipsMmuCommon.c3
-rw-r--r--SylixOS/include/arch/mips/inc/cpu.h3
-rw-r--r--SylixOS/kernel/include/k_kernel.h2
7 files changed, 23 insertions, 4 deletions
diff --git a/SylixOS/arch/mips/common/mipsCpuProbe.c b/SylixOS/arch/mips/common/mipsCpuProbe.c
index 3da69b2..0b1f4d0 100644
--- a/SylixOS/arch/mips/common/mipsCpuProbe.c
+++ b/SylixOS/arch/mips/common/mipsCpuProbe.c
@@ -81,6 +81,10 @@ static VOID mispCpuProbeLegacy (VOID)
_G_uiMipsCpuType = CPU_LOONGSON1;
break;
+ case PRID_REV_LOONGSON3A_R4_0: /* 用 REV 进行判断 */
+ _G_uiMipsCpuType = CPU_LOONGSON3_COMP; /* Loongson-3A4000 */
+ break;
+
case PRID_IMP_CETC_HR2: /* CETC-HR2 */
_G_uiMipsCpuType = CPU_CETC_HR2;
break;
diff --git a/SylixOS/arch/mips/mm/cache/loongson3x/mipsCacheLs3x.c b/SylixOS/arch/mips/mm/cache/loongson3x/mipsCacheLs3x.c
index 1a3378f..74f791e 100644
--- a/SylixOS/arch/mips/mm/cache/loongson3x/mipsCacheLs3x.c
+++ b/SylixOS/arch/mips/mm/cache/loongson3x/mipsCacheLs3x.c
@@ -222,6 +222,11 @@ VOID ls3xCacheFlushAll (VOID)
mipsCpuProbe(MIPS_MACHINE_LS3X); /* MIPS CPU 探测 */
mipsCacheProbe(MIPS_MACHINE_LS3X); /* CACHE 探测 */
+ if (_G_uiMipsPridImp == PRID_REV_LOONGSON3A_R4_0) {
+ ls3aR2CacheFlushAll();
+ return;
+ }
+
switch (_G_uiMipsPridRev) {
case PRID_REV_LOONGSON3A_R2:
diff --git a/SylixOS/arch/mips/mm/cache/mipsCacheCommon.c b/SylixOS/arch/mips/mm/cache/mipsCacheCommon.c
index c7267d2..da7dfe0 100644
--- a/SylixOS/arch/mips/mm/cache/mipsCacheCommon.c
+++ b/SylixOS/arch/mips/mm/cache/mipsCacheCommon.c
@@ -84,6 +84,7 @@ static VOID mipsPCacheProbe (VOID)
break;
case CPU_LOONGSON3:
+ case CPU_LOONGSON3_COMP:
case CPU_LOONGSON2K:
case CPU_CETC_HR2:
uiConfig1 = mipsCp0Config1Read();
@@ -212,6 +213,7 @@ static VOID mipsVCacheProbe (VOID)
_G_VCache.CACHE_bPresent = LW_FALSE;
if ((_G_uiMipsCpuType != CPU_LOONGSON3) && /* Loongson-3x/2G/2H */
+ (_G_uiMipsCpuType != CPU_LOONGSON3_COMP) &&
(_G_uiMipsCpuType != CPU_LOONGSON2K)) { /* Loongson-2K */
return;
}
@@ -358,6 +360,7 @@ static VOID mipsSCacheSetup (VOID)
break;
case CPU_LOONGSON3:
+ case CPU_LOONGSON3_COMP:
case CPU_LOONGSON2K:
case CPU_CETC_HR2:
loongson3SCacheInit();
@@ -453,6 +456,7 @@ VOID mipsCacheProbe (CPCHAR pcMachineName)
break;
case CPU_LOONGSON3: /* Loongson-2G/2H/3x */
+ case CPU_LOONGSON3_COMP:
case CPU_LOONGSON2K: /* Loongson-2K */
case CPU_CETC_HR2: /* CETC-HR2 */
_G_bHaveTagHi = LW_TRUE;
diff --git a/SylixOS/arch/mips/mm/mipsCache.c b/SylixOS/arch/mips/mm/mipsCache.c
index 0da600e..c8e310a 100644
--- a/SylixOS/arch/mips/mm/mipsCache.c
+++ b/SylixOS/arch/mips/mm/mipsCache.c
@@ -47,7 +47,8 @@ VOID archCacheInit (CACHE_MODE uiInstruction, CACHE_MODE uiData, CPCHAR pcMa
mipsCpuProbe(pcMachineName); /* MIPS CPU 探测 */
- if ((_G_uiMipsCpuType == CPU_LOONGSON3) || /* Loongson-3x/2G/2H */
+ if ((_G_uiMipsCpuType == CPU_LOONGSON3) || /* Loongson-3x/2G/2H */
+ (_G_uiMipsCpuType == CPU_LOONGSON3_COMP) ||
(_G_uiMipsCpuType == CPU_LOONGSON2K)) { /* Loongson-2K */
mipsCacheLs3xInit(pcacheop, uiInstruction, uiData, pcMachineName);
@@ -76,7 +77,8 @@ VOID archCacheReset (CPCHAR pcMachineName)
{
mipsCpuProbe(pcMachineName); /* MIPS CPU 探测 */
- if ((_G_uiMipsCpuType == CPU_LOONGSON3) || /* Loongson-3x/2G/2H */
+ if ((_G_uiMipsCpuType == CPU_LOONGSON3) || /* Loongson-3x/2G/2H */
+ (_G_uiMipsCpuType == CPU_LOONGSON3_COMP) ||
(_G_uiMipsCpuType == CPU_LOONGSON2K)) { /* Loongson-2K */
mipsCacheLs3xReset(pcMachineName);
diff --git a/SylixOS/arch/mips/mm/mmu/mipsMmuCommon.c b/SylixOS/arch/mips/mm/mmu/mipsMmuCommon.c
index 1846ba9..05d3273 100644
--- a/SylixOS/arch/mips/mm/mmu/mipsMmuCommon.c
+++ b/SylixOS/arch/mips/mm/mmu/mipsMmuCommon.c
@@ -82,6 +82,7 @@ VOID mipsMmuInvalidateMicroTLB (VOID)
break;
case CPU_LOONGSON3:
+ case CPU_LOONGSON3_COMP:
mipsCp0DiagWrite((LOONGSON_DIAG_DTLB) | /* GS464E 才有 DTLB, GS464 没有*/
(LOONGSON_DIAG_ITLB)); /* 无效 ITLB DTLB */
break;
@@ -226,6 +227,7 @@ static INT mipsMmuGlobalInit (CPCHAR pcMachineName)
}
if ((_G_uiMipsCpuType == CPU_LOONGSON3) || /* Loongson-3x/2G/2H */
+ (_G_uiMipsCpuType == CPU_LOONGSON3_COMP) ||
(_G_uiMipsCpuType == CPU_LOONGSON2K)) { /* Loongson-2K */
UINT32 uiGSConfig = mipsCp0GSConfigRead();
uiGSConfig &= ~(1 << 3); /* Store 操作也进行硬件自动预取*/
@@ -370,6 +372,7 @@ VOID mipsMmuInit (LW_MMU_OP *pmmuop, CPCHAR pcMachineName)
case CPU_LOONGSON1:
case CPU_LOONGSON2:
case CPU_LOONGSON3:
+ case CPU_LOONGSON3_COMP:
case CPU_LOONGSON2K:
_G_bMmuHasXI = LW_TRUE; /* 有执行阻止位 */
_G_uiMmuEntryLoUnCache = 0x2; /* 非高速缓存 */
diff --git a/SylixOS/include/arch/mips/inc/cpu.h b/SylixOS/include/arch/mips/inc/cpu.h
index 8c98f73..c208e36 100644
--- a/SylixOS/include/arch/mips/inc/cpu.h
+++ b/SylixOS/include/arch/mips/inc/cpu.h
@@ -167,6 +167,7 @@
#define PRID_REV_LOONGSON3A_R2 0x0008
#define PRID_REV_LOONGSON3A_R3_0 0x0009
#define PRID_REV_LOONGSON3A_R3_1 0x000D
+#define PRID_REV_LOONGSON3A_R4_0 0xC000
#define PRID_REV_LOONGSON2H 0x0005 /* Same as 3A, 2G */
#define PRID_REV_LOONGSON2G 0x0005 /* Same as 3A, 2H */
@@ -219,7 +220,7 @@ typedef enum cpu_type_enum {
* MIPS64 class processors
*/
CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
- CPU_LOONGSON3, CPU_LOONGSON2K, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+ CPU_LOONGSON3, CPU_LOONGSON2K, CPU_LOONGSON3_COMP, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_CETC_HR2,
CPU_QEMU_GENERIC,
diff --git a/SylixOS/kernel/include/k_kernel.h b/SylixOS/kernel/include/k_kernel.h
index 0356deb..e626b48 100644
--- a/SylixOS/kernel/include/k_kernel.h
+++ b/SylixOS/kernel/include/k_kernel.h
@@ -53,7 +53,7 @@
#define __SYLIXOS_MAJOR_VER 2
#define __SYLIXOS_MINOR_VER 1
-#define __SYLIXOS_PATCH_VER 0
+#define __SYLIXOS_PATCH_VER 1
#define __SYLIXOS_PATCH_PAD 0
/*********************************************************************************************************