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authorHanhui <hanhui@acoinfo.com>2021-02-20 05:33:24 (GMT)
committer Hanhui <hanhui@acoinfo.com>2021-02-20 05:33:24 (GMT)
commitee5fc56069512a03eb64cbefff92cadb57380a27 (patch)
tree9e11d460a5faad5d47a7f20dd7c6292165117dcb /SylixOS
parent21a4b2dccdabee1a9c754343080068124d566ae8 (diff)
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Fastlock add RW lock support.
Diffstat (limited to 'SylixOS')
-rw-r--r--SylixOS/driver/sio/16c550.c5
-rw-r--r--SylixOS/posix/fastlock/rwlock.c3
2 files changed, 8 insertions, 0 deletions
diff --git a/SylixOS/driver/sio/16c550.c b/SylixOS/driver/sio/16c550.c
index 1bd6b03..45dfd69 100644
--- a/SylixOS/driver/sio/16c550.c
+++ b/SylixOS/driver/sio/16c550.c
@@ -619,6 +619,11 @@ static INT sio16c550Hup (SIO16C550_CHAN *psiochan)
{
INTREG intreg;
+ /*
+ * make sure the UART transmitter has completely drained
+ */
+ while (!(GET_REG(psiochan, LSR) & LSR_TEMT));
+
LW_SPIN_LOCK_QUICK(&psiochan->slock, &intreg);
psiochan->mcr &= (~(MCR_RTS | MCR_DTR));
diff --git a/SylixOS/posix/fastlock/rwlock.c b/SylixOS/posix/fastlock/rwlock.c
new file mode 100644
index 0000000..15a5e57
--- /dev/null
+++ b/SylixOS/posix/fastlock/rwlock.c
@@ -0,0 +1,3 @@
+/*
+ * This file NOT include in open source version.
+ */